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NTE6821 Integrated Circuit Peripheral Interface Adapter (PIA), NMOS, 1MHz
Description: The NTE6821 is a peripheral interface adapter (PIA) in a 40-Lead DIP type package capable of interfacing the Microprocessing Unit (MPU) to peripherals through two 8-Bit bidirectional peripheral data buses and four control lines. No external logic is required for interfacing to most peripheral devices. The functional configuration of the PIA is programmed by the MPU during system initialization. Each of the peripheral data lines can be programmed to act as an input or output, and each of the four control/interrupt lines may be programmed for one of several control modes. This allows a high degree of flexibility in the over-all operation of the interface. Features: D 8-Bit Bidirectional Data Bus for Communication with the MPU D Two Bidirectional 8-Bit Buses for Interface to Peripherals D Two Programmed Control Registers D Two Programmed Data Direction Registers D Four Individually-Controlled Interrupt Input Lines; Two Usable as Peripheral Control Outputs D Handshake Control Logic for Input and Output Peripheral Operation D High-Impedance 3-State and Direct Transistor Drive Peripheral Lines D Program Controlled Interrupt and Interrupt Disable Capability D CMOS Drive Capability on Side A Peripheral Lines D Two TTL Drive Capability on All A and B Side Buffers D TTL Compatible D Static Operation Absolute Maximum Ratings: (Note 1) Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +7V Input Voltage, Vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +7V Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +70C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to +150C Thermal Resistance, Junction to Ambient, RJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.5C/W Note 1. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance.
Electrical Characteristics: (VCC = 5V 5%, VSS = 0, TA = 0 to +70C unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit Bus Control Inputs (R/W, Enable, Reset, RS0, RS1, CS0, CS1, CS2) Input High Voltage Input Low Voltage Input Leakage Current Capacitance Interrupt Outputs (IRQA, IRQB) Output Low Voltage Output Leakage Current (Off State) Capacitance Data Bus (D0 - D7) Input High Voltage Input Low Voltage Three-State (Off State) Input Current Output High Voltage Output Low Voltage Capacitance VIH VIL ITSI VOH VOL Cin Iin Vin = 0 to 5.25V ITSI Vin = 0.4 to 2.4V IIH VIH = 2.4V IOH VO = 1.5V IIL VIL = 0.4V VOH ILoad = -200A ILoad = 10A VOL Cin PD ILoad = 3.2mA Vin = 0, TA = +25C, f = 1MHz VSS +2.4 VCC -1.0 - - - - - - - - VSS +0.4 10 V V V pF - -1.3 -2.4 mA -1.0 - -10 mA -200 -400 - - 2.0 10 - 1.0 2.5 Vin = 0.4 to 2.4V ILoad = -205A ILoad = 1.6mA Vin = 0, TA = +25C, f = 1MHz VSS +2.0 VSS -0.3 - VSS +2.4 - - - - 2.0 - - - VCC VSS +0.8 10 - VSS +0.4 12.5 V V A V V pF VOL ILOH Cout ILoad = 3.2mA VOH = 2.4V Vin = 0, TA = +25C, f = 1MHz - - - - 1.0 - VSS +0.4 10 5.0 V A pF VIH VIL Iin Cin Vin = 0 to 5.25V Vin = 0, TA = +25C, f = 1MHz VSS +2.0 VSS -0.3 - - - - 1.0 - VCC VSS +0.8 2.5 7.5 V V A pF
Peripheral Bus (PA0 - PA7, PB0 - PB7, CA1, CA2, CB1, CB2) Input Leakage Current R/W, Reset, RS0, RS1, CS0, CS1, CS2, CA1, CB1, Enable Three-State (Off State) Input Current PB0 - PB7, CB2 Input High Current PA0 - PA7, CA2 Darlington Drive Current PB0 - PB7, CB2 Input Low Current PA0 - PA7, CA2 Output High Voltage PA0 - PA7, PB0 - PB7, CA2, CB2 PA0 - PA7, CA2 Output Low Voltage Capacitance Power Requirements Power Dissipation - - 550 mW A
A A
Bus Timing Characteristics: (VCC = 5V 5%, VSS = 0, TA = 0 to +70C unless otherwise specified)
Parameter Enable Cycle Time Enable Pulse Width, High Enable Pulse Width, Low Enable Pulse Rise and Fall Times Symbol tcycE PWEH PWEL tEr, tEf Test Conditions Min 1000 450 430 - Typ - - - - Max - - - 25 Unit ns ns ns ns
Bus Timing Characteristics (Cont'd): (VCC = 5V 5%, VSS = 0, TA = 0 to +70C unless otherwise specified)
Parameter Setup Time, Address and R/W Valid to Enable Positive Transition Address Hold Time Data Delay Time, Read Data Hold Time, Read Data Setup Time, Write data Hold Time, Write Symbol tAS tAH tDDR tDHR tDSW tDHW Test Conditions Min 160 10 - 10 195 10 Typ - - - - - - Max - - 320 - - - Unit ns ns ns ns ns ns
Peripheral Timing Characteristics:
(VCC = 5V 5%, VSS = 0, TA = 0 to +70C unless otherwise specified)
Symbol tPDSU tPDH tCA2 tRS1 tr, tf tRS2 tPDW tCMOS tCB2 tDC tRS1 PWCT tr, tf tRS2 tIR tRS3 PWI tRL Min 200 0 - - - - - - - 20 - 550 - - - - 500 1.0 Max - - 1.0 1.0 1.0 2.0 1.0 2.0 1.0 - 1.0 - 1.0 2.0 2.0 1.0 - - Unit ns ns s s s s s s s ns s ns s s s s ns s
Parameter Peripheral Data Setup Time Peripheral Data Hold Time Delay Time, Enable negative transition to CA2 negative transition Delay Time, Enable negative transition to CA2 positive transition Rise and fall Times for CA1 and CA2 input signals Delay Time from CA1 active transition to CA2 positive transition Delay Time, Enable negative transition to Peripheral Data Valid Delay Time, Enable negative transition to Peripheral CMOS Data Valid PA0 - PA7, CA2 Delay Time, Enable positive transition to CB2 negative transition Delay Time, Peripheral Data Valid to CB2 negative transition Delay Time, Enable positive transition to CB2 postivie transition Peripheral Control Output Pulse Width, CA2/CB2 Rise and Fall Time for CB1 and CB2 input signals Delay Time, CB1 active transition to CB2 positive transition Interrupt Release Time, IRQA and IRQB Interrupt Response Time Interrupt Input Pulse Width Reset Low Time (Note 2)
Note 2. The Reset line must be high a minimum of 1.0s before addressing the PIA.
Expanded Block Diagram
IRQA 38 Control Register A (CRA) Data Bus Buffers (DBB) Data Direction Register A (DDRA) Output Bus Output Register A (ORA) Input Bus 2 3 4 5 6 7 8 9 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 Interrupt Status Control A 40 CA1 39 CA2
D0 D1 D2 D3 D4 D5 D6 D7
33 32 31 30 29 28 27 26
Peripheral Interface A
Bus Input Register (BIR)
VCC = PIN20 VSS = PIN1 CS0 CS1 CS2 RS0 RS1 R/W Enable Reset 22 24 23 36 35 21 25 34
Output Register B (ORB) Chip Select and R/W Control
Peripheral Interface B
10 11 12 13 14 15 16 17
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7
Control Register B (CRB)
Data Direction Register B (DDRB)
IRQB
37
Interrupt Status Control B
18 CB1 19 CB2
Pin Connection Diagram
VSS 1 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 2 3 4 5 6 7 8 9 40 CA1 39 CA2 38 IRQA 37 IRQB 36 RS0 35 RS1 34 RESET 33 D0 32 D1 31 D2 30 D3 29 D4 28 D5 27 D6 26 D7 25 E 24 CS1 23 CS2 22 CS0 21 R/W
PB0 10 PB1 11 PB2 12 PB3 13 PB4 14 PB5 15 PB6 16 PB7 17 CB1 18 CB2 19 VCC 20
40
21
1 2.055 (52.2)
20 .550 (13.9) Max .155 (3.9)
.100 (2.54)
.019 (0.5)
.137 (3.5)
.650 (16.5)

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